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硅酸盐通报 ›› 2025, Vol. 44 ›› Issue (9): 3451-3461.DOI: 10.16552/j.cnki.issn1001-1625.2025.0172

• 功能材料 • 上一篇    下一篇

超低阻值重掺磷直拉硅界面形状和组分过冷的数值模拟

马武祥1, 梅昊天1, 李晓川2, 范吉祥1, 吴彦国1   

  1. 1.麦斯克电子材料股份有限公司,洛阳 471000;
    2.龙门实验室,洛阳 471000
  • 收稿日期:2025-02-19 修订日期:2025-03-20 出版日期:2025-09-15 发布日期:2025-09-19
  • 作者简介:马武祥(1992—),男,工程师。主要从事半导体级硅单晶生长工艺的研发。E-mail:lymwxiang16@sina.com
  • 基金资助:
    龙门实验室重大科技项目(231100220100)

Numerical Simulation of Interface Shape and Constitutional Supercooling on Heavily Phosphorus-Doped Czochralski Silicon with Ultra-Low Resistivity

MA Wuxiang1, MEI Haotian1, LI Xiaochuan2, FAN Jixiang1, WU Yanguo1   

  1. 1. MCL Electronic Materials Co., Ltd., Luoyang 471000, China;
    2. Longmen Laboratory, Luoyang 471000, China
  • Received:2025-02-19 Revised:2025-03-20 Published:2025-09-15 Online:2025-09-19

摘要: 生产实践中超低阻值重掺磷硅单晶的拉制,主要受限于高浓度掺杂引起的结晶界面处组分过冷和界面形状变化。本文通过CGSIM有限元软件对生产过程中晶体生长长度1 000 mm附近连续出现晶格失配引起位错的情况进行模拟,明确了该阶段产生晶格失配的原因在于生长界面凹度增大及界面处磷杂质浓度的富集引起的组分过冷,并提出了改善方案。结果表明,通过降低晶转、拉晶速率、液口距和增大埚转可以降低界面高度;结合组分过冷条件晶体生长速率V和熔体温度梯度G之间的比值V/G,降低V值进行拉晶,减弱组分过冷的影响。采用优化后的拉晶工艺,获得了连续5炉次超低阻值8英寸(1英寸=2.54 cm)重掺磷无位错硅晶棒,电阻率分布在0.000 93~0.001 25 Ω·cm,进一步证实了模拟结果的有效性。

关键词: 超低阻值, 重掺磷, 硅单晶, 数值模拟, 界面形状, 组分过冷

Abstract: The production of heavily phosphorus-doped silicon single crystals with ultra-low resistivity is primarily constrained by constitutional supercooling induced by high-concentration doping and crystal-melt interface deformation during Czochralski growth. In this study, to investigate the persistent lattice mismatch observed at a crystal length of approximately 1 000 mm during production, simulations were performed using CGSIM finite element software. It was demonstrated that the lattice mismatch originated from the elevation of the crystal-melt interface and phosphorus impurity segregation. And an improvement was proposed. The results indicate that interface height can be reduced by lowering crystal rotation, growth rate, and melt gap, while increasing crucible rotation. Based on the constitutional supercooling criterion V/G (crystal growth rate V divided by melt temperature gradient G), crystal pulling is conducted with a reduced V value to mitigate supercooling effects. By applying optimized parameters, dislocation-free 8-inch (1-inch=2.54 cm) heavily phosphorus-doped silicon single crystals are successfully grown over 5 consecutive cycles. The measured resistivity ranges from 0.000 93 Ω·cm to 0.001 25 Ω·cm, further validating the simulation results.

Key words: ultra-low resistivity, heavily phosphorus doping, silicon single crystal, numerical simulation, interface shape, constitutional supercooling

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